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020 _a9781259253201
040 _aCvSU-CCAT Campus Library.
_bEnglish.
_cCvSU-CCAT Campus Library.
_erda.
050 _aCIR TK 871.99.M44
_bK36 2015
100 _aKang, Sung-Mo, 1945- author.
_92857
245 _aCMOS digital integrated circuits :
_banalysis and design /
_cSung-Mo (Steve) Kang, Yusuf Leblebici, Chulwoo Kim.
250 _aFourth edition.
260 _aNew York, New York :
_bMcGraw-Hill Education,
_cc2015.
300 _axviii, 714 pages, 8 variously numbered pages of plates :
_billustrations ;
_c24 cm.
490 _aComplementary metal oxide semiconductor digital integrated circuits
504 _aIncludes bibliographical references and index.
505 _aMachine-generated contents note: ch. 1 Introduction -- 1.1. Historical Perspective -- 1.2. Objective and Organization of the Book -- 1.3. A Circuit Design Example -- 1.4. Overview of VLSI Design Methodologies -- 1.5. VLSI Design Flow -- 1.6. Design Hierarchy -- 1.7. Concepts of Regularity, Modularity, and Locality -- 1.8. VLSI Design Styles -- 1.9. Design Quality -- 1.10. Packaging Technology -- 1.11. Computer-Aided Design Technology -- Exercise Problems -- ch. 2 Fabrication of MOSFETs -- 2.1. Introduction -- 2.2. Fabrication Process Flow: Basic Steps -- 2.3. The CMOS n-Well Process -- 2.4. Evolution of CMOS Technology -- 2.5. Layout Design Rules -- 2.6. Full-Custom Mask Layout Design -- Exercise Problems -- ch. 3 MOS Transistor -- 3.1. The Metal Oxide Semiconductor (MOS) Structure -- 3.2. The MOS System Under External Bias -- 3.3. Structure and Operation of the MOS Transistor (MOSFET) -- 3.4. MOSFET Current-Voltage Characteristics -- 3.5. MOSFET Scaling and Small-Geometry Effects -- 3.6. MOSFET Capacitances -- Exercise Problems -- ch. 4 Modelling of MOS Transistors Using SPICE -- 4.1. Introduction -- 4.2. Basic Concepts -- 4.3. The Level 1 Model Equations -- 4.4. The Level 2 Model Equations -- 4.5. The Level 3 Model Equations -- 4.6. State-of-the-Art MOSFET Models -- 4.7. Capacitance Models -- 4.8. Comparison of the SPICE MOSFET Models -- Appendix: Typical SPICE Model Parameters -- Exercise Problems -- ch. 5 MOS Inverters: Static Characteristics -- 5.1. Introduction -- 5.2. Resistive-Load Inverter -- 5.3. Inverters with MOSFET Load -- 5.4. CMOS Inverter -- Appendix: Sizing Trends of CMOS Inverter with Small-Geometry Devices -- Exercise Problems -- ch. 6 MOS Inverters: Switching Characteristics and Interconnect Effects -- 6.1. Introduction -- 6.2. Delay-Time Definitions -- 6.3. Calculation of Delay Times -- 6.4. Inverter Design with Delay Constraints -- 6.5. Estimation of Interconnect Parasitics -- 6.6. Calculation of Interconnect Delay -- 6.7. Switching Power Dissipation of CMOS Inverters -- Appendix: Super Buffer Design -- Exercise Problems -- ch. 7 Combinational MOS Logic Circuits -- 7.1. Introduction -- 7.2. MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads -- 7.3. CMOS Logic Circuits -- 7.4. Complex Logic Circuits -- 7.5. CMOS Transmission Gates (Pass Gates) -- Exercise Problems -- ch. 8 Sequential MOS Logic Circuits -- 8.1. Introduction -- 8.2. Behaviour of Bistable Elements -- 8.3. The SR Latch Circuit -- 8.4. Clocked Latch and Flip-Flop Circuits -- 8.5. Timing-Related Parameters of Clocked Storage Elements -- 8.6. CMOS D-Latch and Edge-Triggered Flip-Hop -- 8.7. Pulsed Latch-Based Clocked Storage Elements -- 8.8. Sense-Amplifier-Based Flip-Flops -- 8.9. Logic Embedding in Clocked Storage Elements -- 8.10. Power Consumption of Clocking System and Power Savings Methodologies -- Appendix -- Exercise Problems -- ch. 9 Dynamic Logic Circuits -- 9.1. Introduction -- 9.2. Basic Principles of Pass Transistor Circuits -- 9.3. Voltage Bootstrapping -- 9.4. Synchronous Dynamic Circuit Techniques -- 9.5. Dynamic CMOS Circuit Techniques -- 9.6. High-Performance Dynamic CMOS Circuits -- Exercise Problems -- ch. 10 Semiconductor Memories -- 10.1. Introduction -- 10.2. Dynamic Random Access Memory (DRAM) -- 10.3. Static Random Access Memory (SRAM) -- 10.4. Non-volatile Memory -- 10.5. Flash Memory -- 10.6. Ferroelectric Random Access Memory (FRAM) -- Exercise Problems -- ch. 11 Low-Power CMOS Logic Circuits -- 11.1. Introduction -- 11.2. Overview of Power Consumption -- 11.3. Low-Power Design Through Voltage Scaling -- 11.4. Estimation and Optimization of Switching Activity -- 11.5. Reduction of Switched Capacitance -- 11.6. Adiabatic Logic Circuits -- Exercise Problems -- ch. 12 Arithmetic Building Blocks -- 12.1. Introduction -- 12.2. Adder -- 12.3. Multipliers -- 12.4. Shifter -- Exercise Problems -- ch. 13 Clock and I/O Circuits -- 13.1. Introduction -- 13.2. ESD Protection -- 13.3. Input Circuits -- 13.4. Output Circuits and L(di/dt) Noise -- 13.5. On-Chip Clock Generation and Distribution -- 13.6. Latch-Up and Its Prevention -- Appendix: Network-on-Chip: An Emerging Paradigm for Next-Generation SoCs -- Exercise Problems -- ch. 14 Design for Manufacturability -- 14.1. Introduction -- 14.2. Process Variations -- 14.3. Basic Concepts and Definitions -- 14.4. Design of Experiments and Performance Modelling -- 14.5. Parametric Yield Estimation -- 14.6. Parametric Yield Maximization -- 14.7. Worst-Case Analysis -- 14.8. Performance Variability Minimization -- Exercise Problems -- ch. 15 Design for Testability -- 15.1. Introduction -- 15.2. Fault Types and Models -- 15.3. Controllability and Observability -- 15.4. Ad Hoc Testable Design Techniques -- 15.5. Scan-Based Techniques
546 _aIn English text.
650 _aMetal oxide semiconductors, Complementary.
_92858
650 _aDigital integrated circuits.
_92859
700 _aLeblebici, Yusuf, author.
_92860
700 _aKim, Chulwoo, author.
_92861
942 _cBK
_eFourth edition.
_hTK 871.99.M44 K36 2015
_kCIR
_2lcc
999 _c973
_d973