Digital principles and logic design / (Record no. 998)

MARC details
000 -LEADER
fixed length control field 07096nam a22002897a 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20231013225811.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 210502b ||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9789814253055
040 ## - CATALOGING SOURCE
Language of cataloging English.
Transcribing agency CvSU-CCAT Campus Library.
Description conventions rda
Original cataloging agency CvSU-CCAT Campus Library.
050 ## - LIBRARY OF CONGRESS CALL NUMBER
Classification number CIR TK 454
Item number S24 2008
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Saha, A., author.
9 (RLIN) 2973
245 ## - TITLE STATEMENT
Title Digital principles and logic design /
Statement of responsibility, etc. A. Saha and N. Manna.
250 ## - EDITION STATEMENT
Edition statement Philippine edition.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Hingham, Mass. :
Name of publisher, distributor, etc. Infinity Science Press,
Date of publication, distribution, etc. c2008.
300 ## - PHYSICAL DESCRIPTION
Extent xi, 384 pages :
Other physical details illustrations ;
Dimensions 20 cm
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes index.
505 ## - FORMATTED CONTENTS NOTE
Formatted contents note CONTENTS Preface (xiii) 1. DATA AND NUMBER SYSTEMS 1<br/>1.1 Introduction 1.2 Number Systems 2<br/>1.3 Conversion between Number Systems 1.4 Complements 10<br/>1.5 Binary Arithmetic 13<br/>1.6 1's And 2's Complement Arithmetic 17<br/>1.7 Signed Binary Numbers 19<br/>1.8 7's And 8's Complement Arithmetic 21<br/>1.9 9's And 10's Complement Arithmetic 23<br/>1.10 15's And 16's Complement Arithmetic 25<br/>1.11 BCD Addition 27<br/>1.12 BCD Subtraction 28<br/>Review Questions 30<br/>2. CODES AND THEIR CONVERSIONS 31<br/>2.1 Introduction 31<br/>2.2 Codes 31<br/>2.3 Solved Problems 44<br/>Review Questions 49<br/>3. BOOLEAN ALGEBRA AND LOGIC GATES 51<br/>3.1 Introduction 51<br/>3.2 Basic Defi nitions 51<br/>3.3 Definition of Boolean Algebra 52<br/>3.4 Two-valued Boolean Algebra 5<br/>3.5 Basic Properties And Theorems of Boolean Algebra 55 <br/>3.6 Venn Diagram 57 <br/>3.7 Boolean Functions 58 <br/>3.8 Simplification of Boolean Expressions 59 <br/>3.9 Canonical And Standard Forms 60 <br/>3.10 Other Logic Operators 67 <br/>3.11 Digital Logic Gates 66 <br/>3.12 Positive And Negative Logic 82 <br/>3.13 Concluding Remarks 83 Review Questions 84 <br/>4. SIMPLIFICATION AND MINIMIZATION OF BOOLEAN FUNCTIONS 87 <br/>4.1 Introduction<br/>4.2 Two-variable Karnaugh Maps<br/>4.3 Three-variable Karnaugh Maps<br/>4.4 Four-variable Karnaugh Maps<br/>4.5 Five-variable Karnaugh Maps<br/>4.6 Six-variable Karnaugh Maps <br/>4.7 Don't-care Combinations <br/>4.8 The Tabulation Method <br/>4.9 More Examples<br/>4.10 Variable-entered Karnaugh Maps<br/>4.11 Concluding Remarks Review Questions<br/>5. COMBINATIONAL LOGIC CIRCUITS <br/>5.1 Introduction <br/>5.2 Design Procedure <br/>5.3 Adders <br/>5.4 Subtractors <br/>5.5 Code Conversion <br/>5.6 Parity Generator And Checker <br/>5.7 Some Examples of Combinational Logic Circuits 141 <br/>5.8 Combinational Logic with MSI And LSI 154 <br/>5.9 Four-bit Binary Parallel Adder 155 <br/>5.10 Magnitude Comparator 165<br/>5.11 Decoders 166<br/>5.12 Encoders 172<br/>5.13 Multiplexers or Data Selectors 173<br/>5.14 Demultiplexers or Data Distributors 186<br/>5.15 Concluding Remarks 188<br/>Review Questions 188<br/>6. PROGRAMMABLE LOGIC DEVICES 190<br/>6.1 Introduction 190<br/>6.2 PLD Notation 192<br/>6.3 Read Only Memory (ROM) 192<br/>6.4 Programmable Logic Array (PLA) 199<br/>6.5 Programmable Array Logic (PAL) Devices 205<br/>6.6 Registered PAL Devices<br/>6.7 Configurable PAL Devices<br/>6.8 Generic Array Logic Devices<br/>6.9 Field-Programmable Gate Array (FPGA)<br/>6.10 Concluding Remarks<br/>Review Questions<br/>7. SEQUENTIAL LOGIC CIRCUITS<br/>7.1 Introduction 211 <br/>7.2 Flip-flops 212 <br/>7.3 Types of Flip-flops 214 <br/>7.4 Clocked S-R Flip-flop 217 <br/>7.5 Clocked D Flip-flop 221 <br/>7.6 J-K Flip-flop 224 <br/>7.7 T Flip-flop 229 <br/>7.8 Toggling Mode of S-R and D Flip-fl ops 231 <br/>7.9 Triggering of Flip-fl ops 231 <br/>7.10 Excitation Table of a Flip-fl op 233 <br/>7.11 Interconversion of Flip-fl ops 233 <br/>7.12 Sequential Circuit Model 244 <br/>7.13 Classification of Sequential Circuits 244 <br/>7.14 Analysis of Sequential Circuits 246 <br/>7.15 Design Procedure of Sequential Circuits 250 <br/>Review Questions<br/>8. REGISTERS 258 8.1<br/>Introduction 258 8.2<br/>Shift Register 258 8.3<br/>Serial-in-Serial-out Shift Register 259 8.4<br/>Serial-in-Parallel-out Register 264 8.5<br/>Parallel-in-Serial-out Register 265 8.6<br/>Parallel-in-Parallel-out Register 267 8.7<br/>Universal Register 269 8.8<br/>Shift Register Counters 271 8.9<br/>Sequence Generator 274 8.10<br/>Serial Addition 278 8.11<br/>Binary Divider 279 Review Questions<br/>284 9. COUNTERS 285 9.1 Introduction<br/>285 9.2 Asynchronous (Serial or Ripple) Counters 286<br/>9.3 Asynchronous Counter ICs 296<br/>9.4 Synchronous (Parallel) Counters 303<br/>9.5 Synchronous Down-Counter 305<br/>9.6 Synchronous Up-Down Counter 306<br/>9.7 Design Procedure of Synchronous Counter 307<br/>9.8 Synchronous/Asynchronous Counter 319<br/>9.9 Presettable Counter 320<br/>9.10 Synchronous Counter ICs 321<br/>9.11 Counter Applications 329<br/>9.12 Hazards in Digital Circuits 332<br/>Review Questions 338<br/>10. A/D AND D/A CONVERSION 339<br/>10.1 Introduction 339<br/>10.2 Digital-to-Analog Converters (DAC) 339<br/>10.3 Specification of D/A Converters 349<br/>10.4 An Example of a D/A Converter 351<br/>10.5 Analog-to-Digital Converters 354<br/>10.6 Specification of an A/D Converter 36<br/>10.7 An Example of an A/D Converter IC<br/>10.8 Concluding Remarks<br/>Review Questions<br/>11. LOGIC FAMILY<br/>11.1 Introduction<br/>11.2 Characteristics of Digital IC<br/>11.3 Bipolar Transistor Characteristics<br/>11.4 Resistor-Transistor Logic (RTL)<br/>11.5 Diode Transistor Logic (DTL)<br/>11.6 Transistor Transistor Logic (TTL)<br/>11.7 Emitter-Coupled Logic (ECL)<br/>11.8 Integrated-Injection Logic (I2L)<br/>11.9 Metal Oxide Semiconductor (MOS)<br/>11.10 Comparison of Different Logic Families<br/>11.11 Interfacing<br/>11.12 Some Examples<br/>Review Questions<br/>Appendix 1: Alternate Gate Symbols<br/>Appendix 2: 74 Series Integrated Circuits <br/>Appendix 3: Pin Configuration of 74 Series Integrated Circuits 431<br/>Appendix 4: 4000 Series Integrated Circuits 451<br/>Appendix 5: Pin Configuration of 4000 Series Integrated Circuits 457<br/>Glossary 473<br/>Bibliography 000<br/>Index 477
520 ## - SUMMARY, ETC.
Summary, etc. "This text / reference provides students and practicing engineers with an introduction to the classical methods of designing electrical circuits, but incorporates modern logic design techniques used in the latest microprocessors, microcontrollers, microcomputers, and various LSI components. The book provides a review of the classical methods e.g., the basic concepts of Boolean algebra, combinational logic and sequential logic procedures, before engaging in the practical design approach and the use of computer-aided tools. The book is enriched with numerous examples (and their solutions), over 500 illustrations, and includes a CD-ROM with simulations, additional figures, and third party software to illustrate the concepts discussed in the book. Key features: Designed as a text/reference to provide students and practicing engineers with information on both classical methods and modern industry applications, Modern applications are discussed in detail, including Karnaugh maps, PLD notation (PAL, PLA, FPGA) and more, Covers fundamental topics as Boolean algebra, logic gates, flip-flops, minimization, etc., CD-ROM includes simulations and third-party software." -- Publisher<br/>
546 ## - LANGUAGE NOTE
Language note In English text.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electric circuits
Form subdivision Design and construction.
9 (RLIN) 2974
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Digital electronics.
9 (RLIN) 2975
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic design.
9 (RLIN) 2751
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Manna, N., author.
9 (RLIN) 2976
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Book
Edition Philippine edition.
Classification part TK 454 S24 2008
Call number prefix CIR
Source of classification or shelving scheme Library of Congress Classification
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Collection code Home library Current library Shelving location Date acquired Source of acquisition Coded location qualifier Full call number Barcode Date last seen Copy number Price effective from Koha item type Total Checkouts Total Renewals Date last checked out
    Library of Congress Classification     Book Cavite State University - CCAT Campus Cavite State University - CCAT Campus GCS 09/12/2011 Purchased GCS CIR TK 454 S24 2008 R0010323 10/15/2025 c.1 05/02/2021 Book      
    Library of Congress Classification     Book Cavite State University - CCAT Campus Cavite State University - CCAT Campus GCS 09/12/2011 Purchased GCS CIR TK 454 S24 2008 R0010324 10/15/2025 c.2 10/11/2023 Book 2 12 03/19/2025
    Library of Congress Classification     Book Cavite State University - CCAT Campus Cavite State University - CCAT Campus GCS 09/12/2011 Purchased GCS CIR TK 454 S24 2008 R0010325 10/15/2025 c.3 10/11/2023 Book