CMOS digital integrated circuits : (Record no. 973)

MARC details
000 -LEADER
fixed length control field 05970nam a22002897a 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20231014014909.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 210415b ||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781259253201
040 ## - CATALOGING SOURCE
Original cataloging agency CvSU-CCAT Campus Library.
Language of cataloging English.
Transcribing agency CvSU-CCAT Campus Library.
Description conventions rda.
050 ## - LIBRARY OF CONGRESS CALL NUMBER
Classification number CIR TK 871.99.M44
Item number K36 2015
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Kang, Sung-Mo, 1945- author.
9 (RLIN) 2857
245 ## - TITLE STATEMENT
Title CMOS digital integrated circuits :
Remainder of title analysis and design /
Statement of responsibility, etc. Sung-Mo (Steve) Kang, Yusuf Leblebici, Chulwoo Kim.
250 ## - EDITION STATEMENT
Edition statement Fourth edition.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. New York, New York :
Name of publisher, distributor, etc. McGraw-Hill Education,
Date of publication, distribution, etc. c2015.
300 ## - PHYSICAL DESCRIPTION
Extent xviii, 714 pages, 8 variously numbered pages of plates :
Other physical details illustrations ;
Dimensions 24 cm.
490 ## - SERIES STATEMENT
Series statement Complementary metal oxide semiconductor digital integrated circuits
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references and index.
505 ## - FORMATTED CONTENTS NOTE
Formatted contents note Machine-generated contents note: ch. 1 Introduction -- 1.1. Historical Perspective -- 1.2. Objective and Organization of the Book -- 1.3. A Circuit Design Example -- 1.4. Overview of VLSI Design Methodologies -- 1.5. VLSI Design Flow -- 1.6. Design Hierarchy -- 1.7. Concepts of Regularity, Modularity, and Locality -- 1.8. VLSI Design Styles -- 1.9. Design Quality -- 1.10. Packaging Technology -- 1.11. Computer-Aided Design Technology -- Exercise Problems -- ch. 2 Fabrication of MOSFETs -- 2.1. Introduction -- 2.2. Fabrication Process Flow: Basic Steps -- 2.3. The CMOS n-Well Process -- 2.4. Evolution of CMOS Technology -- 2.5. Layout Design Rules -- 2.6. Full-Custom Mask Layout Design -- Exercise Problems -- ch. 3 MOS Transistor -- 3.1. The Metal Oxide Semiconductor (MOS) Structure -- 3.2. The MOS System Under External Bias -- 3.3. Structure and Operation of the MOS Transistor (MOSFET) -- 3.4. MOSFET Current-Voltage Characteristics -- 3.5. MOSFET Scaling and Small-Geometry Effects -- 3.6. MOSFET Capacitances -- Exercise Problems -- ch. 4 Modelling of MOS Transistors Using SPICE -- 4.1. Introduction -- 4.2. Basic Concepts -- 4.3. The Level 1 Model Equations -- 4.4. The Level 2 Model Equations -- 4.5. The Level 3 Model Equations -- 4.6. State-of-the-Art MOSFET Models -- 4.7. Capacitance Models -- 4.8. Comparison of the SPICE MOSFET Models -- Appendix: Typical SPICE Model Parameters -- Exercise Problems -- ch. 5 MOS Inverters: Static Characteristics -- 5.1. Introduction -- 5.2. Resistive-Load Inverter -- 5.3. Inverters with MOSFET Load -- 5.4. CMOS Inverter -- Appendix: Sizing Trends of CMOS Inverter with Small-Geometry Devices -- Exercise Problems -- ch. 6 MOS Inverters: Switching Characteristics and Interconnect Effects -- 6.1. Introduction -- 6.2. Delay-Time Definitions -- 6.3. Calculation of Delay Times -- 6.4. Inverter Design with Delay Constraints -- 6.5. Estimation of Interconnect Parasitics -- 6.6. Calculation of Interconnect Delay -- 6.7. Switching Power Dissipation of CMOS Inverters -- Appendix: Super Buffer Design -- Exercise Problems -- ch. 7 Combinational MOS Logic Circuits -- 7.1. Introduction -- 7.2. MOS Logic Circuits with Pseudo-nMOS (pMOS) Loads -- 7.3. CMOS Logic Circuits -- 7.4. Complex Logic Circuits -- 7.5. CMOS Transmission Gates (Pass Gates) -- Exercise Problems -- ch. 8 Sequential MOS Logic Circuits -- 8.1. Introduction -- 8.2. Behaviour of Bistable Elements -- 8.3. The SR Latch Circuit -- 8.4. Clocked Latch and Flip-Flop Circuits -- 8.5. Timing-Related Parameters of Clocked Storage Elements -- 8.6. CMOS D-Latch and Edge-Triggered Flip-Hop -- 8.7. Pulsed Latch-Based Clocked Storage Elements -- 8.8. Sense-Amplifier-Based Flip-Flops -- 8.9. Logic Embedding in Clocked Storage Elements -- 8.10. Power Consumption of Clocking System and Power Savings Methodologies -- Appendix -- Exercise Problems -- ch. 9 Dynamic Logic Circuits -- 9.1. Introduction -- 9.2. Basic Principles of Pass Transistor Circuits -- 9.3. Voltage Bootstrapping -- 9.4. Synchronous Dynamic Circuit Techniques -- 9.5. Dynamic CMOS Circuit Techniques -- 9.6. High-Performance Dynamic CMOS Circuits -- Exercise Problems -- ch. 10 Semiconductor Memories -- 10.1. Introduction -- 10.2. Dynamic Random Access Memory (DRAM) -- 10.3. Static Random Access Memory (SRAM) -- 10.4. Non-volatile Memory -- 10.5. Flash Memory -- 10.6. Ferroelectric Random Access Memory (FRAM) -- Exercise Problems -- ch. 11 Low-Power CMOS Logic Circuits -- 11.1. Introduction -- 11.2. Overview of Power Consumption -- 11.3. Low-Power Design Through Voltage Scaling -- 11.4. Estimation and Optimization of Switching Activity -- 11.5. Reduction of Switched Capacitance -- 11.6. Adiabatic Logic Circuits -- Exercise Problems -- ch. 12 Arithmetic Building Blocks -- 12.1. Introduction -- 12.2. Adder -- 12.3. Multipliers -- 12.4. Shifter -- Exercise Problems -- ch. 13 Clock and I/O Circuits -- 13.1. Introduction -- 13.2. ESD Protection -- 13.3. Input Circuits -- 13.4. Output Circuits and L(di/dt) Noise -- 13.5. On-Chip Clock Generation and Distribution -- 13.6. Latch-Up and Its Prevention -- Appendix: Network-on-Chip: An Emerging Paradigm for Next-Generation SoCs -- Exercise Problems -- ch. 14 Design for Manufacturability -- 14.1. Introduction -- 14.2. Process Variations -- 14.3. Basic Concepts and Definitions -- 14.4. Design of Experiments and Performance Modelling -- 14.5. Parametric Yield Estimation -- 14.6. Parametric Yield Maximization -- 14.7. Worst-Case Analysis -- 14.8. Performance Variability Minimization -- Exercise Problems -- ch. 15 Design for Testability -- 15.1. Introduction -- 15.2. Fault Types and Models -- 15.3. Controllability and Observability -- 15.4. Ad Hoc Testable Design Techniques -- 15.5. Scan-Based Techniques
546 ## - LANGUAGE NOTE
Language note In English text.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Metal oxide semiconductors, Complementary.
9 (RLIN) 2858
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Digital integrated circuits.
9 (RLIN) 2859
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Leblebici, Yusuf, author.
9 (RLIN) 2860
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Kim, Chulwoo, author.
9 (RLIN) 2861
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Book
Edition Fourth edition.
Classification part TK 871.99.M44 K36 2015
Call number prefix CIR
Source of classification or shelving scheme Library of Congress Classification
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Collection code Home library Current library Shelving location Date acquired Source of acquisition Coded location qualifier Cost, normal purchase price Full call number Barcode Date last seen Copy number Price effective from Koha item type
    Library of Congress Classification     Book Cavite State University - CCAT Campus Cavite State University - CCAT Campus GCS 09/15/2015 Purchased GCS 2733.00 CIR TK 871.99.M44 K36 2015 R0011125 10/15/2025 1 04/15/2021 Book